1. Field of the Invention
The present invention generally relates to timing adjustment circuits used in clock synchronous apparatuses, and particularly relates to a timing adjustment circuit for adjusting the timing of clock synchronization of a data input/output interface.
2. Description of the Related Art
FIG. 1 is an illustrative drawing showing an example of a construction in which semiconductor chips of the clock synchronous type are connected to each other. Chips 10 through 13 shown in FIG. 1 operate in synchronization with a clock signal. A data signal output from the chip 10 in synchronization with the clock signal is input into the chips 11 through 13. In respect of this, the setup time and hold time of the input signal, the maximum delay of the output signal, etc., are defined relative to the timing of the clock signal. The chips 10 through 13 are required to perform the inputting/outputting of the data signal at the timing that satisfies these specifications.
Semiconductor devices are bound to have manufacturing variation. The input/output cells for inputting/outputting data signals have delay fluctuation due to such manufacturing variation. Conventionally, such delay fluctuation has not been much of a problem. When the operation speed of semiconductor devices is increased by increasing the frequency of a clock signal, however, the problem of delay fluctuation of the input/output cells becomes apparent. Namely, if the input/output cells have delay fluctuation under the condition of high operating frequency, the setup time and hold time of input signals, the maximum delay of output signals, etc. may not be able to meet their requirements. This may result in a failure of data exchange between the chips. Further, there is an effect of differences in flight time caused by the differences of path lengths between the chips, and also an effect of an increase of the load caused by the connection of multiple chips to a single output node. These effects make it difficult to conduct reliable data exchange.
FIG. 2 is a circuit diagram showing an example of a timing adjustment circuit that corrects the timing of an input/output interface of the clock synchronous type. A timing adjustment circuit 20 of FIG. 2 includes a clock input circuit 21, a PLL (phase locked loop) circuit 22, a clock tree 23, a feedback tree 24, a flip-flop 25 for signal output, a input-purpose flip-flop 26 for signal input, a data output circuit 27, and a data input circuit 28.
The clock input circuit 21 receives a clock signal Clock supplied from the exterior of the chip, and supplies the received signal to the PLL circuit 22 as an input clock signal ck0. The clock input circuit 21 has an inherent delay time A. The input clock signal ck0 includes a delay equal to the delay time A relative to the clock signal Clock when supplied to the PLL circuit 22. The PLL circuit 22 adjusts the phase of the input clock signal ck0, and outputs a clock signal ckr having the adjusted phase. The clock signal ckr having the adjusted phase propagates through the clock tree 23 before it is supplied to the output-purpose flip-flop 25 and the input-purpose flip-flop 26 as a synchronizing clock signal ck1. Moreover, the clock signal ckr having the adjusted phase is supplied to another input of the PLL circuit 22 as a delayed clock signal ckf through the feedback tree 24, which has the same delay C′ as the delay C of the clock tree 23. The PLL circuit 22 performs phase control such that the input clock signal ck0 and the delayed clock signal ckf have the same phase, thereby generating the clock signal ckr having the adjusted phase.
The output-purpose flip-flop 25 outputs output data d0 at edge timing of the synchronizing clock signal ck1. The output data d0 is output to the exterior of the chip as a data output signal DataOut by the data output circuit 27. The data output circuit 27 has an inherent delay time B, so that the data output signal DataOut has a delay equal to the delay time B relative to the output data d0.
The data input circuit 28 receives a data input signal DataIn supplied from the exterior of the chip, and supplies the received signal to the input-purpose flip-flop 26 as input data d1. The input-purpose flip-flop 26 latches the input data d1 at edge timing of the synchronizing clock signal ck1. The data input circuit 28 has an inherent delay time A, so that the input data d1 has a delay equal to the delay time A relative to the data input signal DataIn. The delay time of the data input circuit 28 and the delay time of the clock input circuit 21 are identical.
FIG. 3 is a timing chart showing the operation timing of the timing adjustment circuit 20 shown in FIG. 2. As shown in FIG. 3, the input clock signal ck0 is delayed by a delay equal to the delay time A relative to the clock signal Clock. The clock signal ckr having an adjusted phase is phase-adjusted such that the delayed clock signal ckf and the input clock signal ck0 have the same phase. Since the delay time C′ of the delayed clock signal ckf is equal to the delay time C of the synchronizing clock signal ck1, the phase of the synchronizing clock signal ck1 coincides with the phase of the input clock signal ck0.
The input data d1 is latched at the edge timing of the synchronizing clock signal ck1. The delay of the synchronizing clock signal ck1 relative to the clock signal Clock and the delay of the input data d1 relative to the data input signal DataIn are the same delay time A. It follows that when the data input signal DataIn is supplied in synchronization with the clock signal Clock, the setup time and hold time are fixed regardless of the length of the delay time A. In this manner, the timing adjustment circuit 20 of FIG. 2 achieves data inputting at fixed timing free from the influence of manufacturing variation.
In FIG. 3, the timing at which the data output signal DataOut is output is delayed by a delay equal to the delay time B relative to the synchronizing clock signal ck1, i.e., is delayed by the delay time A+B relative to the clock signal Clock. This data output signal DataOut propagates from the chip 10 to the chip 20 as shown in FIG. 1, for example, by spending a flight time FT before receipt by the chip 20 as the data input signal DataIn. If the delay time A+B of the data output signal DataOut increases due to manufacturing variation, the input timing of the data input signal DataIn at the chip 20 is delayed proportionately. In this case, a sufficient setup time cannot be secured, which may result in a data input error.
FIG. 4 is a circuit diagram showing another example of the timing adjustment circuit that corrects the timing of an input/output interface of the clock synchronous type. In FIG. 4, the same elements as those of FIG. 2 are referred to by the same numerals, and a description thereof will be omitted.
A timing adjustment circuit 20A of FIG. 4 is provided with a dummy input/output circuit 29 in addition to the configuration of the timing adjustment circuit 20 shown in FIG. 2. The dummy input/output circuit 29 includes a dummy input circuit 21A having the same delay time A as the clock input circuit 21 and a dummy output circuit 27A having the same delay time B as the data output circuit 27. The dummy input/output circuit 29 thus has a total delay time equal to A+B. The dummy input/output circuit 29 is inserted into the feedback path for phase control, so that the delayed clock signal ckf input into the PLL circuit 22 has a delay time equal to A+B+C′ relative to the clock signal ckr having the adjusted phase.
FIG. 5 is a timing chart showing the operation timing of the timing adjustment circuit 20A of FIG. 4. As shown in FIG. 5, the input clock signal ck0 is delayed by a delay equal to the delay time A relative to the clock signal Clock. The clock signal ckr having an adjusted phase is phase-adjusted such that the delayed clock signal ckf and the input clock signal ck0 have the same phase. The delayed clock signal ckf is delayed by the delay time A+B+C′ relative to the clock signal ckr having the adjusted phase, and the data output signal DataOut is output with the delay C+B relative to the clock signal ckr having the adjusted phase. Accordingly, the data output signal DataOut is output a time A earlier than the delayed clock signal ckf. Since this delayed clock signal ckf is delayed by the delay time A relative to the clock signal Clock, the output timing of the data output signal DataOut is equal to the edge timing of the clock signal Clock. This timing match is maintained even if the delay times A, B, and/or C fluctuate due to manufacturing variation.
This data output signal DataOut propagates from the chip 10 to the chip 20 as shown in FIG. 1, for example, by spending a flight time FT before receipt by the chip 20 as the data input signal DataIn. The timing of the data output signal DataOut is fixed relative to the clock signal Clock regardless of manufacturing variation, so that the timing of the data input signal DataIn received at the chip 20 is also fixed to the clock signal Clock. Accordingly, this provision makes it possible to secure a proper setup time so as to attain reliable data inputting.
At the data input side of the timing adjustment circuit 20A shown in FIG. 4, the input data d1 is latched at the edge timing of the synchronizing clock signal ck1. The input data d1 is delayed by the delay time A relative to the data input signal DataIn, whereas the synchronizing clock signal ck1 is time B earlier than the clock signal Clock. (The synchronizing clock signal ck1 is delayed by the time A relative to the clock signal Clock in FIG. 3, but is time A+B earlier than this timing where the time A+B is the delay time of the dummy input/output circuit 29.) When the data input signal DataIn is supplied in synchronization with the clock signal Clock, the setup time and hold time fluctuate due to the variation of the time A and time B, resulting in difficulty securing the required timing conditions.
Patent Document 1 discloses an example in which a timing adjustment circuit for correcting the timing of an input/output interface of the clock synchronous type is applied to a memory device.
[Patent Document 1] Japanese Patent Application Publication No. 10-112182
If a timing adjustment circuit attends to timing control such as to have data-input timing that is not affected by manufacturing variation as described above, the timing of data outputs ends up being affected by manufacturing variation, resulting in a data-receiver-side semiconductor device failing to secure proper input timing. On the other hand, if a timing adjustment circuit attends to timing control such as to have data-output timing that is not affected by manufacturing variation, the timing of data inputs ends up being affected by manufacturing variation, resulting in a failure to secure proper input timing.
Accordingly, there is a need for a timing adjustment circuit that can achieve proper operating timing with respect to both the data input and the data output regardless of manufacturing variation.